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L9942
Integrated stepper motor driver for bipolar stepper motors with microstepping and programmable current profile
PRELIMINARY DATA
Features

Two full bridges for max. 1.3 A load (RDSON = 500 m) Programmable current waveform with look-up table: 9 entries with 5bit resolution Current regulation by integrated PWM controller and internal current sensing Programmable stepping mode: Full, Half, Mini and Microstepping Programmable slew rate for EMC and power dissipation optimisation Programmable Fast-, Slow-, Mixed-and AutoDecay Mode Full-Scale Current programmable with 3bit resolution Very low current consumption in standby mode IS < 3A, typ. Tj 85 C All outputs short circuit protected with Openload, Overloadcurrent, Temperature Warning and Thermal Shutdown The PWM signal of the internal PWM controller is available as digital output. All parameters guaranteed for 7V < Vs < 20V
PowerSSO-24
Description
The device is an integrated stepper motor driver for bipolar stepper motors with microstepping and programmable current profile look-up-table to allow a flexible adaptation of the stepper motor characteristics and intended operating conditions. It is possible to use different current profiles depending on target criteria: audible noise, vibrations, rotation speed or torque. The decay mode used in PWM-current control circuit can be programmed to slow-, fast-, mixed-and autodecay. In autodecay mode device will use slow decay mode if the current for the next step will increase and the fast decay or mixed decay mode if the current will decrease.

Applications
Stepper Motor Driver for bipolar Stepper Motors in Automotive Applications like Light Levelling, Bending Light and Throttle Control.
Order codes
Part number L9942 Junction Temp range, C -40 to 150 Package PowerSSO-24 Packing Tube
November 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev 1 1/37
www.st.com
37
L9942
Contents
1 2 Block diagram and Pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Dual Power Supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Standby-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Over-voltage and Under-voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Temperature Warning and Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . 6 Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PWM Current Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Over Current Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Stepping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Decay Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 3.2 3.3 3.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Over- and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reference Current Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Charge Pump Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Outputs: Qxn (x=A;B n=1;2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Outputs: Qxn (x=A;B n=1;2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Functional Description of the Logic with SPI . . . . . . . . . . . . . . . . . . . . . . 19
4.1 4.2 Motor Stepping Clock Input( STEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PWM Output (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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L9942 4.3 4.4 4.5 4.6 4.7 4.8 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
SPI - Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Counter and Profiles Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Signal and Profile Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Counter and Profile (Register 4 and Register 5) . . . . . . . . . . . . . . . . . . . . . . 23 Control, Status and Profile Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Status Register7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Auxiliary logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.8.1 5.8.2 5.8.3 Fault Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SPI communication monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PWM monitoring for stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6
Logic with SPI - Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 6.2 6.3 6.4 6.5 6.6 Inputs: CSN, CLK, STEP, EN and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Outputs: DO, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Output: DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 STEP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1 7.2 Stall Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Load Current Control and Detection of Overcurrent (Shortages at Outputs) 31
8 9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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1 Block diagram and Pin information
L9942
1
Block diagram and Pin information
Figure 1. Block diagram
VBAT VCC
CP
Oscillator STEP EN Phase Counter+Current Profile PWM Current DAC PWM SPI + Register + Logic Charge Pump
Diagnostic
ReversePolarityProtection VS Note: value of capacitor has to be choosen carefully to limit the VS voltage below absolute maximum ratings in case of an unexpected freewheeling condition (e.g. TSD, POR)
QA1
Gate-Driver & PWM-Controller
QA2
Stepper Motor
C
DO
DI CLK CSN
QB1
Gate-Driver & PWM-Controller
Diagnostic
QB2
Biasing
U/IConverter RREF
GND
GNDP
GND
Figure 2.
Pin connection (Top view)
PGND
1
Power SSO24
24 PGND 23 QA2 22 VS 21 EN 20 RREF
QA1 2 VS 3 CLK 4 DI 5 CSN 6 DO 7 PWM 8 STEP 9 VS 10 QB1 11 PGND 12
All pins with the same name must be externally connected! All pins PGND are internally connected to the heat slug.
Slugdown
19 VCC 18 TEST 17 GND 16 CP 15 VS 14 QB2 13 PGND
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L9942
Table 1.
Pin 1, 12, 13, 24
1 Block diagram and Pin information
Pin Description
Symbol PGND Function Power ground: All pins PGND are internally connected to the heat slug. Important: All pins of PGND must be externally connected! Power supply voltage (external reverse protection required): For EMI reason a ceramic capacitor as close as possible to PGND is recommended. Important: All pins of VS must be externally connected !
3, 10, 15, 22
VS
2, 23
Fullbridge-outputs An: The output is built by a highside and a lowside switch, which are internally connected. The output stage of both switches is a power QA1,QA2 DMOS transistor. Each driver has an internal reverse diode (bulk-drain-diode: highside driver from output to VS, lowside driver from PGND to output). This output is over-current protected. Fullbridge-outputs Bn: The output is built by a highside and a lowside switch, which are internally connected. The output stage of both switches is a power QB1,QB2 DMOS transistor. Each driver has an internal reverse diode (bulk-drain-diode: highside driver from output to VS, lowside driver from PGND to output). This output is over-current protected. CLK SPI clock input: The input requires CMOS logic levels. The CLK input has a pull-down current. It controls the internal shift register of the SPI. Serial data input: The input requires CMOS logic levels. The DI input has a pull-down current. It receives serial data from the microcontroller. The data is a 16bit control word and the least significant bit (LSB, bit 0) is transferred first. Chip Select Not input The input requires CMOS logic levels. The CSN input has a pull-up current. The serial data transfer between device and micro controller is enabled by pulling the input CSN to low level. SPI data output: The diagnosis data is available via the SPI and it is a tristateoutput. The output is CMOS compatible will remain highly resistive, if the chip is not selected by the input CSN (CSN = high) PWM output This CMOS compatible output reflects the current duty cycle of the internal PWM controller of bridge A. It is an high resistance output until VCC has reached minimum voltage ore can switched off via the SPI command. Step clock input: The input requires CMOS logic levels. The STEP input has a pull-down current. It is clock of up and down counter of control register 0. Rising edge starts new PWM cycle to drive motor in next position. Charge Pump Output: A ceramic capacitor (e.g.100 nF) to VS can be connected to this pin to buffer the charge-pump voltage. Ground: Reference potential besides power ground e.g. for reference resistor RREF. From this pin exist a resistive path via substrate to PGND. Test input The TEST input has a pull-down current. Pin used for production test only. In the application it must be connected to GND. Logic supply voltage: For this input a ceramic capacitor as close as possible to GND is recommended. Reference Resistor The reference resistor is used to generate a temperature stable reference current used for current control and internal oscillator. At this output a voltage of about 1.28V is present. The resistor should be chosen that a current of about 200uA will flow through the resistor. Enable input: The input requires CMOS logic levels. The EN input has a pulldown resistor. In standby-mode outputs will be switched off and all registers will be cleared. If EN is set to a logic high level then the device will enter the active mode.
11, 14
4
5
DI
6
CSN
7
DO
8
PWM
9
STEP
16 17 18 19
CP GND TEST VCC
20
RREF
21
EN
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2 Device description
L9942
2
2.1
Device description
Dual Power Supply: VS and VCC
The power supply voltage VS supplies the half bridges. An internal charge-pump is used to drive the highside switches. The logic supply voltage VCC (stabilized) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-on (VCC increases from under voltage to VPOR OFF = 2.60 V, typical) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases under the minimum threshold (VPOR ON = 2.45 V, typical), the outputs are switched to tristate (high impedance) and the internal registers are cleared.
2.2
Standby-Mode
The EN input has a pull-down resistor. The device is in standby mode if EN input isn't set to a logic high level. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at VS (VCC) is less than 3 A (1A) for CSN = high (DO in tristate). If EN is set to a logic high level then the device will enter the active mode. In the active mode the chargepump and the supervisor functions are activated.
2.3
Diagnostic Functions
All diagnostic functions (overload/-current, open load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered (tGL = 32s, typical) and the condition has to be valid for a minimum time before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. Open load and temperature warning function are intended for information purpose and will not change the state of the bridge drivers. On contrary, the overload/-current and thermal shutdown condition will disable the corresponding driver (overload/-current) or all drivers (thermal shutdown), respectively. The microcontroller has to clear the status bit to reactivate the bridge driver.
2.4
Over-voltage and Under-voltage Detection
If the power supply voltage VS rises above the over-voltage threshold VSOV OFF (typical 20 V), the outputs are switched to high impedance state to protect the load. When the voltage VS drops below the undervoltage threshold VSUV OFF (UV-switch-OFF voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). Error condition is lached and the microcontroller needs to clear the status bits to reactivate the drivers.
2.5
Temperature Warning and Thermal Shutdown
If junction temperature rises above Tj TW a temperature warning flag is set which is detectable via the SPI. If junction temperature increases above the second threshold Tj SD, the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to
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L9942
2 Device description
protect the device. In order to reactivate the output stages the junction temperature must decrease below Tj SD -Tj SD HYS and the thermal shutdown bit has to be cleared by the microcontroller.
2.6
Inductive Loads
Each half bridge is built by an internally connected highside and a lowside power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven without external free-wheeling diodes. In order to reduce the power dissipation during free-wheeling condition the PWMcontroller will switch-on the output transistor parallel to the freewheeling diode (synchronous rectification).
2.7
Cross-current protection
The four half-brides of the device are cross-current protected by an internal delay time depending on the programmed slew rate. If one driver (LS or HS) is turned-off then activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time .
2.8
PWM Current Regulation
An internal current monitor output of each high-side and low-side transistor sources a current image which has a fixed ratio of the instantaneous load current. This current images are compared with the current limit in PWM control. Range of limit can reach from programmed full scale value (register1 DAC Scale) down belonging LSB value of 5 bit DAC (register1 DAC Phase x). The data of the two 5 bit DACs comes form set up in 9 current profiles (register2 to 6). If signal changes to logic high at pin STEP then 2 currentprofiles are moved in register1 for DAC Phase A and B. Number of profile depends on phase counter reading and direction bit in register0 (Figure 7). The bridges are switched on until the load current sensed at HS switch exceeds the limit . Load current comparator signal is used to detect open load or overcurrent condition also.
2.9
Decay modes
During off-time the device will use one of several decay modes programmable by SPI (Figure 4 top). In slow decay mode HS switches are activated after cross current protection time for synchronous rectification to reduce the power dissipation (Figure 4 detail A). In fast decay opposite halfbridge will switched on after cross current protection time, that is same like change in the direction. For mixed decay the duration of fast decay period before slow decay can be set to a fixed time (Figure 4 detail B continuous line ) or is triggered by under-run of the load current limit (Figure 4 detail B dashed line), that can be detected at LS switch. The special mode where the actual phase counter value is taken into account to select the decay mode is called auto decay (e.g. in Figure 3 Micro Stepping DIR=1). If the absolute value of the current limit is higher as during step before then PWM control uses slow decay mode always. Otherwise one of the fast decay modes is automatic selected for a quick decrease of the load current and so it obtains new lower target value.
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2 Device description
L9942
2.10
Over Current Detection
The overcurrent detection circuit monitors the load current in each activated output stage. In HS stage it is in function after detection of currentlimit during PWM cycle and in LS stage it works permanently. If the load current exceeds the overcurrent detection threshold for at least tISC = 4 s, the over-current flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. Error condition is lached and the microcontroller needs to clear the status bits to reactivate the drivers.
2.11
Open Load Detection
The open load detection monitors the activity time of the PWM controller and is available for each phase. If the limit of load current is below around 100mA then open load condition is detectable. Open load bit for a bridge is set in the register6 if this low current limit can't reached after at least 15 consecutive PWM cycles. Table 2.
DC2 0 0 0 1 1 1 1 1
Truth table
DC1 0 0 1 1 0 0 1 1 DC0 0 1 0 0 0 1 0 1 I4 0 0 0 0 0 0 0 0 I3 x x 0 0 0 0 0 0 I2 x x x x 0 0 0 0 I1 x x x x x x 0 0 I0 x x x x x x 1 1 max. IOL 48mA 72mA 56mA 90mA 58mA 87mA 42mA 48mA
Truth table shows possible profiles for active open load detection. Maximum threshold IOL is shown in left column if x bits are 1 (see also Figure 7). Lowest possible limit is e.g. 3.1 mA for DC2=DC1=DC0=0 and it is set only I0=1.
2.12
Stepping Modes
One full revolution can consist of four full steps, eight half steps, sixteen mini steps or 32 microsteps. Mode is set up in register 0 and it defines increment size of phase counter. Phase counter value defines address of corresponding currentprofile. Stepping modes with typical profile values can see in Figure 3 (e.g. also so called 'Two Phase On' shown in dashed line).
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L9942
Figure 3.
0
2 Device description
Stepping Modes
Full-Stepping Mode: DIR=0
8 16 24
Full-Stepping Mode: DIR=1
Phase Counter
24 16 8 0
Current Driver A
0 8 0 8
Current Driver A
Address of Current Profile Entry
0 8 0 8
Current Driver B Current Driver B
8 0 8 0
Address of Current Profile Entry
8
0
8
0
STEP Signal
STEP Signal
Half-Stepping Mode: DIR=0
0 4 8 12 16 20 24 28
Half-Stepping Mode: DIR=1
Phase Counter
0 28 24 20 16 12 8 4
Current Driver A
0 4 8 4 0 4 8 4
Driver Current A
Address of Current Profile Entry
0 4 8 4 0 4 8 4
Current Driver B
8 4 0 4 8 4 0 4
Driver Current B
Address of Current Profile Entry
8 4 0 4 8 4 0 4
STEP Signal
STEP Signal
Mini-Stepping Mode: DIR=0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
Mini-Stepping Mode: DIR=1
Phase Counter
0 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
Current Driver A
Adress of Current Profile Entry
Current Driver A
4 6 8 6 4 2 0 2 4 6 8 6 4 2 0 2 4 6 8 6 4 2
0
2
4
6
8
6
4
2
0
2
Current Driver B
8 6 4 2 0 2 4 6 8 6 4 2 0 2 4 6
Current Driver B
Adress of Current Profile Entry
8 6 4 2 0 2 4 6 8 6 4 2 0 2 4 6
STEP Signal
STEP Signal
Micro Stepping Mode: DIR=0 (e.g auto decay)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Micro Stepping Mode: DIR=1 (e.g. auto decay)
Phase Counter
0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Current Driver A
Slow Decay Mode Slow Decay Mode Mixed Decay Mode Mixed Decay Mode Adress of Current Profile Entry Slow Decay Mode
Current Driver A
Mixed Decay Mode Slow Decay Mode Mixed Decay Mode
01234567876543210123456787654321
01234567876543210123456787654321
Mixed Decay Mode
Current Driver B
Slow Decay Mode Mixed Decay Mode
Slow Decay Mode Adress of Current Profile Entry
Mixed Decay Mode
Current Driver B
Slow Decay Mode Mixed Decay Mode
Slow Decay Mode
87654321012345678765432101234567
87654321012345678765432101234567
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2 Device description
L9942
2.13
Figure 4.
Decay Modes
Decay Modes
Load Current
ON
SLOW DECAY
FAST DECAY
VS
MIXED DECAY
VS on on
A
VS on on VS on VS on
on
B
on
on
Time Internal PWM_CLK
fast decay
Load Current Step Limit HS
Detail A: SWITCH ON AND SLOW DECAY
ON T FT TCC SLOW DECAY
register0 DM2 DM1 DM0 0 0 0 MODE slow
VS
fast decay
TB TCC TFT TCC TB
Time
Fast decay is caused by current through internal diodes during cross current protection time.
OFF
OFF
OFF
OFF
Filter time for the purpose of switch off delay in on mode is set by FT register6 Cross current protection time is set by SR1 SR0 register0 Blank time of load current comparator TB=TCC
Detail B: MIXED DECAY
register0
DM2 DM1 DM0 MODE CURVE
X X X Load Current TCC Step Limit LS TFT
0 1 1
1 0 1
T MD1 T MD2 T mc Load Current
TCC
SLOW DECAY after current undershoot
T MDx= TMD1 or T MD2
TCC
FAST DECAY
Tmc
FAST DECAY
T MDx
SLOW DECAY with delay
> T mc = T FT + 2TCC
TCC Time
Time TFT Filter time for purpose of delay when decay mode has to change after limit under-run TMD When limit is reached so fast decay duration time is set by DM1 DM2 register0
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L9942
3 Electrical specifications
3
3.1
Electrical specifications
Absolute maximum ratings
Table 3.
Symbol VS
Absolute maximum ratings
Parameter Value -0.3...28 40 -0.3 to 5.5 Unit V V V
DC supply voltage single pulse tmax < 400 ms
VCC VDI,VDO, VCLK VCSN, VSTEP VEN VRREF VCP VQxn IQxn
stabilized supply voltage, logic supply digital input / output voltage
-0.3 to VCC + 0.3
V
current reference resistor charge pump output (x=A;B n=1;2) output voltage (x=A;B n=1;2) output current
-0.3 to VCC + 0.3 -0.3 to VS + 11 -0.3 to VS + 0.3 2.5
V V V A
Note:
Leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit !
3.2
ESD Protection
Table 4. ESD Protection
Parameter All pins output pins: Qxn (x=A;B n=1;2) Value Unit kV kV
2 1 4 2
Note: 1 HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A 2 HBM with all unzapped pins grounded
3.3
Thermal data
Table 5.
Symbol
Operating junction temperature
Parameter operating junction temperature Value -40 to 150 Unit C
Tj
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3 Electrical specifications
L9942
Table 6.
Symbol TjTW ON
Temperature warning and thermal shutdown
Parameter temperature warning threshold junction temperature temperature warning threshold junction temperature thermal shutdown thresholdjunction temperature thermal shutdown threshold junction temperature thermal shutdown hysteresis 150 5 Tj increasing 130 170 Min. Typ. Max. 150 Unit C C C C K
TjTW OFF
TjSD ON TjSD OFF TjSD HYS
Figure 5.
Thermal data of package
Note: 1s 1 signal layer 2s2p 2 signal layers 2 internal planes
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L9942
3 Electrical specifications
3.4
3.4.1
Electrical characteristics
Supply
VS = 7 to 16V, VCC = 3.0 to 5.3 V, Tj = -40 to 150 C, IREF = -200 A , unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.
Table 7.
Symbol
Supply
Parameter VS DC supply current in active mode Test Condition VS = 13.5 V, EN=VCC outputs floating Tj = -40 C VS = 13.5 V, TEST, to 25C EN = 0V outputs floating Tj = 125 C VCC = 5.0 V EN=VCC, DI=CLK=STEP=0V Min. Typ. 7 3 6 1 Max. 20 10 A 20 3 mA Unit mA
IS VS quiescent supply current
ICC
VCC DC supply current in active mode
VCC = 5.0 V TEST; Tj = -40 C EN = 0V; CSN = VCC no clocks to 25C outputs floating CSN=VCC no clocks outputs floating Tj = 125 C
1
3
A
2
6
A
ICC
VCC quescent suppy current
VS = 13.5 V, VCC = Tj = -40 C 5.0 V to 25C TEST; EN=0V CSN=VCC no Sum quiescent supply current clocks outputs floating VCC on set up time
4
13 A
IS + ICC
Tj = 125 C
8
26
tsetPOR 1
EN = 5V, CSN=CLK=0V DO changes from high ohmic to logic level LOW
2
s
Note: 1 This parameter is guaranteed by design.
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3 Electrical specifications
L9942
3.4.2
Over- and undervoltage detection
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 C, IREF = -200 A, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.
Table 8.
Symbol VSUV ON VSUV OFF VSUV hyst VSOV OFF VSOV ON VSOV hyst VPOR OFF VPOR ON VPOR hyst
Over- and undervoltage detection .
Parameter VS UV-threshold voltage VS UV-threshold voltage VS UV-hysteresis VS OV-threshold voltage VS OV-threshold voltage VS OV-hysteresis power-on-reset threshold power-on-reset threshold power-on-reset hysteresis Test Condition VS increasing VS decreasing VSUV ON -VSUV OFF VS increasing VS decreasing VSOV OFF -VSOV ON VCC increasing VCC decreasing VPOR OFF -VPOR ON 2.00 20 0.5 2.6 2.3 0.11 2.9 4.8 0.3 25 Min. Typ. Max. 6.90 Unit V V V V V V V V V
Figure 6.
VS Monitoring
Register 7 OV
Register 7 UV
1
1
0
VSUV OFF VSUV ON
0 VS
VSOV ON VSOV OFF
VS
3.4.3
Reference Current Output
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 C, IREF = -200 A, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.
Table 9.
Symbol VREF IREFshorted IREFopen
Reference Current Output
Parameter reference voltage range Test Condition IREF = -200 A Min. 1.05 Typ. 1.25 Max. 1.45 -250 -150 Unit V A A
reference current register6 bit7 RERR = 1 threshold shorted pin REF reference current threshold open pin REF register6 bit7 RERR = 1
The device works properly without the external resistor at pin REF. In this case it doesn't have to fullfill all specified parameters.
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L9942
3 Electrical specifications
3.4.4
Charge Pump Output
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 C, IREF = -200 A, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.
Table 10. Symbol
VCP
Charge Pump Output Parameter
charge pump output voltage
Test Condition
VS=7V VS=13.5V VS=20V ICP= -100A, all switches off at Qxn
Min.
11 20 30
Typ.
Max.
20 35 40
Unit
V V V
The ripple of voltage at CP can suppressed using a capicity of e.g.100nF.
3.4.5
Outputs: Qxn (x=A;B n=1;2)
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 C, IREF = -200 A, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin
Table 11.
Symbol
Outputs: Qxn (x=A;B n=1;2)
Parameter Test Condition VS = 13.5 V, Tj = 25 C, IQxn = -1.0A Min. Typ. 500 Max. 700 Unit m
RDSON HS
on-resistance Qxn to VS
VS = 13.5 V, Tj = 125 C, IQxn = -1.0 A VS = 7.0 V, Tj = 25 C, IQxn = -1.0 A VS = 13.5 V, Tj = 25 C, IQxn = + 1.0A
750
1000
m
550
750
m
500
700
m
RDSON LS
on-resistance Qxn to PGND
VS = 13.5 V, Tj = 125 C, IQxn = + 1.0 A VS = 7.0 V, Tj = 25 C, IQxn = + 1.0 A
750
1000
m
550
750
m
|IQxnOC |
output overcurrent limitation to VS or PGND
testmode exclusive of filtertime 4us (Chapter 2.10)
1.6
2
A
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3 Electrical specifications
L9942
3.4.6
Outputs: Qxn (x=A;B n=1;2)
The comparator, which is monitoring current image of HS, is working during ON cycle of PWM control. If load current is higher as set value then the signal ILIMIT is generated and after filter time the bridge is switched off. Test mode gets access to signal ILIMIT and threshold of current can be measured.
Table 12.
Outputs: Qxn (x=A;B n=1;2) VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 C, IREF = -200 A, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin
Parameter Test Condition Bits: DC2 DC1 DC0=000 Bits: DC2 DC1 DC0=001 Min. 60 100 180 300 485 720 1000 1200 MIN2 Typ. 95 140 230 360 550 810 1150 1350 Max. 130 180 280 420 mA Bits: DC2 DC1 DC0=100 Bits: DC2 DC1 DC0=101 Bits: DC2 DC1 DC0=110 Bits: DC2 DC1 DC0=111 615 900 1300 1500 MAX2 mA Unit
Symbol
IQxnFS_HS
Value of output current to supply VS ( so called full scale value)1 sourcing from HS switch
Bits: DC2 DC1 DC0=010 Bits: DC2 DC1 DC0=011
IQxnLIM_HS
Accuracy of micro steps current limit
Note: 1 Current profile has to pre set with I4 I3 I2 I1 I0 = 11111 and load to register 1 . 2 MIN= 0.92 * IQxnLIM - 0.02 * |IQxnFS_HS | , MAX= 1.08 * IQxnLIM + 0.02 * |IQxnFS_HS |
Output current limit IQxnLIM is product of full scale current |IQxnFS_ | ( bits DC2 DC1 DC0) and value of DAC PhaseA/B ( bits I4 I3 I2 I1 I0) in register1. Values of DAC Phase A and B can read out and depends on set up done before: 1. 2. direction DIR , stepping mode ST1 ST0 and phase counter P4 P3 P2 P1 P0 in register 0 and value of corresponding current profile (for address of current profile entry see also Figure 3).
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Figure 7. Logic to Set Load Current Limit
3 Electrical specifications
UP/Down Count by 1,2,4,8
Register 0
PhaseCounter
P4 P3 P2 P1 P0 Decay Mode DM2 DM1 DM0 Slew Rate SR1 SR0
StepMode
ST1 ST0
DIR
STEP
0 0 0
012 30 123 01 23
A2 A1 A0
MUX MUX
MUX
A3
A2
A1
A0
Address Calculation Phase B
A3=0 neg(A[3..0]) A3=1 Adr A[3..0]
Phase A
Adr A3=0 A[3..0] Adr A3=1 neg(A[3..0]) Adr
Current-Profile Table stored in register2, ...6
9
5
I4 I4 I4 I4 I4 I4 I4 I4 I4
I3 I3 I3 I3 I3 I3 I3 I3 I3
I2 I2 I2 I2 I2 I2 I2 I2 I2
I1 I1 I1 I1 I1 I1 I1 I1 I1
I0 I0 I0 I0 I0 I0 I0 I0 I0
Profile 8 Profile 7 Profile 6 Profile 5 Profile 4 Profile 3 Profile 2 Profile 1 Profile 0
5
Register 1
DAC Scale DAC Phase B DAC Phase A
5
DI
DC2 DC1 DC0 I4
I3
I2
I1
I0
I4
I3
I2
I1
I0 QA1 I QA1LIM 1000
5 5 bit DAC Phase B LIMIT B 5 bit DAC Phase A
5
I LIMIT A
I Qx1LIM QA2
5
REF
I REF
DAC Full Scale
I MAX I QB1LIM 1000
5
5
QB1
5
IQA2LIM 1000 I Qx2LIM QB2 IQB2LIM 1000
5
3.4.7
PWM Control
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 C, IREF = -200 A, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.
Table 13.
Symbol fPWM 1 TMD1 TFT1
PWM Control (see Figure 4 and Figure 7)
Parameter Frequency of PWM cycles Bit: FRE= 0 Bits: DM1 DM0= 0 1 Mixed decay switch off delay time Bits: DM1 DM0= 1 0 Bit: FILTER= 0 Glitch filter delay time Bit: FILTER= 1 2.5 us 8 1.5 us us 31.3 4 kHz us Test Condition Bit: FRE= 1 Min. Typ. 20.8 Max. Unit kHz
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L9942
Table 13.
Symbol
PWM Control (see Figure 4 and Figure 7) (continued)
Parameter Test Condition Bits: SR1 SR0= 0 0 Min. Typ. 0.5 1 2 4 13 13 6 6 Max. Unit us us us us V/us V/us V/us V/us
Tcc 1 TB
1
Cross current protection time Blank Bits: SR1 SR0= 0 1 time of comparator Bits: SR1 SR0= 1 0 Bits: SR1 SR0= 1 1 Bits: SR1 SR0= 0 0
VSR
Slew rate (dV/dt 30%-70%) @HS switches on resistive load of 10, VS=13.5V
Bits: SR1 SR0= 0 1 Bits: SR1 SR0= 1 0 Bits: SR1 SR0= 1 1
Note: 1 This parameter is guaranteed by design. Time base is an internal trimmed oscillator of typical 2MHz and it has an accuracy of 6% .
Figure 8. Switching on Minimum Time
Load current at Qxn T FT Filter time of current comparator T FT TCC T
CC
Cross current protection time
T B Blank time of current comparator Step limit e.g. T B = TCC = 1 us T FT = 1.5 us
T CC Internal PWM clock 20 or 30 kHz TINT _2MHz Pin PWM (for bridge A)
TB Time TPWM on decay
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4 Functional Description of the Logic with SPI
4
4.1
Functional Description of the Logic with SPI
Motor Stepping Clock Input( STEP)
Rising edge of signal STEP is latched. It is synchronised by internal clock. At next start of a new PWM cycle the new values of output current limit are used to drive motor in next position. Before start new motor step this signal has to be low for at least two internal clock periods to reset latch.
4.2
PWM Output (PWM)
This output reflects the current duty cycle of the internal PWM controller of bridge A. High level indicates on state to increase current through load and low level is in off state so load current decreases depending on chosen decay mode.
4.3
Serial Peripheral Interface (SPI)
This device uses a standard 16 bit SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect an internal Error Flag of the device which is a logical-or of all status bits in the Status Register (reg7) and in the Current Profile Register 4 (reg6). The microcontroller can poll the status of the device without the need of a full SPI-communication cycle.
4.4
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN will be called a communication frame.
4.5
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and latched into an internal 16 bit shift register. The first 3 bit are interpreted as address of the data register. At the rising edge of the CSN signal the contents of the shift register will be transferred to the selected data register. The writing to the register is only enabled if exactly 16 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.
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4 Functional Description of the Logic with SPI
L9942
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.
4.6
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.
4.7
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal.
4.8
Data Register
The device has eight data registers. The first three bits (bit0 ... bit2) at the DI-input are used to select one of the input registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected Input Data Register only if a frame of exact 16 data bits are detected. The selected register will be transferred to DO during the current communication frame.
Figure 9.
SPI and Registers
DI DO D0 D1 A1 D2 A2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 A0 A1 A2
CLK
D
CSN INT_2MHz POR SPIControll
CLK_ADR SEL_ERROR SPI2REG
D A0
Phase Counter
Decay Mode P1 P0 DM2 DM1 DM0
Slew Rate SR1 SR0
Step Mode ST1 ST0 DIR
Control Register 0
P4
P3
P2
Read Only DAC_Scale
Control Register 1 Counter and Profiles Register 2 Singnal and Profiles Register 3 Counter and Profiles Register 4 Counter and Profiles Register 5 Control, Status and Profile Register 6 Status Register 7
DC2
DC1 DC0
BI4
BI3
DAC Phase B BI2 BI1
BI0
AI4
DAC Phase A AI3 AI2 AI1
AI0
I4
Current Profile 1 I3 I2 I1
Test I0 T2
PWM Counter DT1 DT0 I4
Current Profile 0 I3 I2 I1
I0
I4
Current Profile 3 I3 I2 I1
Test I0 T5 T4
PWM NPWM T3
I4
Current Profile 2 I3 I2 I1
I0
Current Profile 5 I4 I3 I2 I1 I0
PWM Counter DT4 DT3 DT2 I4
Current Profile 4 I3 I2 I1
I0
Current Profile 7 I4 I3 I2 I1 I0
PWM Counter DT7 DT6 DT5 I4
Current Profile 6 I3 I2 I1
I0
CLR Status SST
Filter
PWM Freq
ST
Read-Only Openload RREF Error Phase Phase B A Read-Only
I4
Current Profile 8 I3 I2 I1
I0
CLR Temperature Status TSD TW
VS Monitor OV UV HSB2 HSB1 LSB2
Overcurrent LSB1 HSA2 HSA1 LSA2 LSA1
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5 SPI - Control and Status Registers
5
5.1
Bit
SPI - Control and Status Registers
Control Register 0
Phase Counter 12 11 rw 0 P3 10 rw 0 P2 9 rw 0 P1 8 rw 0 P0 7 rw 0 DM2 Decay Mode 6 rw 0 DM1 5 rw 0 DM0 Slew Rate 4 rw 0 SR1 3 rw 0 SR0 Step Mode 2 rw 0 ST1 1 rw 0 ST0 DIR 0 rw 0 DIR
Access Reset Name
rw 0 P4
The meaning of the different bits is as follows:
DIR This bit controls direction of motor movement. DIR=1 clockwise DIR=0 counter clockwise.
ST1 ST0 00 01 10 11
This bits controls step mode of motor movement (Figure 3). Micro-stepping Mini-stepping Half-stepping Full-stepping
SR1 SR0
This bit controls slew rate of bridge switches. See also parameter Table 13
DM2 DM1 DM0 000 001 010 011 100 101 110 111
This bits controls decay mode of output current (Figure 3). Slow decay Mixed decay, fast decay until TMD > 4us Mixed decay, fast decay until TMD > 8us Mixed decay, fast decay until current undershoot Tmc =TFT +TCC Auto decay, fast decay without delay time Auto decay, fast decay until TMD > 4us Auto decay, fast decay until TMD > 8us Auto decay, fast decay until current undershoot Tmc Auto decay uses mixed decay automatically to reduce current for next step if required ( see Figure 3 down right).
P4 P3 P2 P1 P0
This bits control position of motor, e.g. 00000 step angle is 0, 01111 step angle is 180..
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5 SPI - Control and Status Registers
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5.2
Bit
Control Register 1
DAC Scale 12 11 rw 0 DC1 10 rw 0 DC0 9 r 0 BI4 8 r 0 BI3 DAC Phase B 7 r 0 BI2 6 r 0 BI1 5 r 0 BI0 4 r 0 AI4 3 r 0 AI3 DAC Phase A 2 r 0 AI2 1 r 0 AI1 0 r 0 AI0
Access Reset Name
rw 0 DC2
The meaning of the different bits is as follows:
AI4 AI3 AI2 AI1 AI0 BI4 BI3 BI2 BI1 BI0 These bits control DAC of bridge A. These bits control DAC of bridge B . These bits set full scale range of limit, e.g. 000 for 100 mA or 111for e.g. 1500mA Value depends on address and the value of corresponding current profile.
DC2 DC1 DC0
See also parameter Table 12.
5.3
Bit
Counter and Profiles Register 2
Current Profile 1 12 11 rw 0 I3 10 rw 0 I2 9 rw 0 I1 8 rw 0 I0 7 rw 0 T2 Not used 6 rw 0 T1 5 rw 0 T0 4 rw 0 I4 Current Profile 0 3 rw 0 I3 2 rw 0 I2 1 rw 0 I1 0 rw 0 I0
Access Reset Name
rw 0 I4
The meaning of the different bits is as follows:
I4 I3 I2 I1 I0 T2 T1 T0 These bits are loaded in register1 DAC Phase A or B if needed. See also parameter Table 12 These bits are used in test mode only.
5.4
Bit
Signal and Profile Register 3
Current Profile 3 12 11 r w 0 I3 10 r w 0 I2 9 r w 0 I1 8 r w 0 I0 PWM Counter 7 r w 0 D1 (T5) 6 r w 0 D0 (T4) PWM 5 r w 0 NPW M(T3) 4 r w 0 I4 Current Profile 2 3 r w 0 I3 2 r w 0 I2 1 r w 0 I1 0 r w 0 I0
Access
r w
Reset Name
0 I4
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L9942
The meaning of the different bits is as follows:
I4 I3 I2 I1 I0 DT1 DT0 NPWM (T5 T4 T3)
5 SPI - Control and Status Registers
These bits are loaded in register1 DAC Phase A or B if needed. These bits are for threshold value in counter of active time during signal PWM. This bit switches internal PWM signal of bridge A to pin PWM if it is set to 0, otherwise pin is in high resistance status. These bits are used in test mode only.
See also parameter Table 12
5.5
Bit
Counter and Profile (Register 4 and Register 5)
Current Profile 5 (7) 12 11 rw 0 I3 10 rw 0 I2 9 rw 0 I1 8 rw 0 I0 7 rw 0 D4(7) PWM Counter 6 rw 0 D3(6) 5 rw 0 D2(5) 4 rw 0 I4 Current Profile 4 (6) 3 rw 0 I3 2 rw 0 I2 1 rw 0 I1 0 rw 0 I0
Access Reset Name
rw 0 I4
The meaning of the different bits is as follows:
I4 I3 I2 I1 I0 These bits are loadedneeded. in register1 DAC Phase A or B if needed. during signal PWM. LSB and next value are set in register3 by D0 and D1. See also parameter Table 12
D4 D3 D2 (register4) These bits are for threshold value in counter of active time
D7 D6 D5 (register5)
5.6
Control, Status and Profile Register 6
CLR
ST Filter (PWM)
11 rw 0 SST 10 rw 0 FT
Freq 9 rw 0 FRE
ST 8 r 0 ST
REF
ERR
7 r 0 RERR
Openload 6 r 0 OB 5 r 0 OA 4 rw 0 I4
Current Profile 8 3 rw 0 I3 2 rw 0 I2 1 rw 0 I1 0 rw 0 I0
Bit Access Reset Name
12 rw 0 CLR6
The meaning of the different bits is as follows:
I4 I3 I2 I1 I0 OB OA RERR ST FRE These bits are loaded in register1 DAC Phase A or B if needed These bits indicate openload at bridges This bit indicates if reference current is OK (150uA 23/37
5 SPI - Control and Status Registers
L9942
FT SST CLR6
This bit sets filter time in glitch filter. FT=0 TF =1.5us, FT=1 TF =2.5us This bit specifies output PWM to reflect same logical level like bit ST. This bit resets all bits to 0 in register 6.
5.7
Bit
Status Register7
CLR 12 Temperature 11 r 0 TSD 10 r 0 TW VS Monitor 9 r 0 OV 8 r 0 UV 7 r 0 6 r 0 5 r 0 LSB2 Overcurrent 4 r 0 LSB1 3 r 0 HSA2 2 r 0 HSA1 1 r 0 LSA2 0 r 0 LSA1
Access Reset Name
rw 0 CLR7
HSB2 HSB1
The meaning of the different bits is as follows:
bit7 ... bit0 1 These bits indicate overcurrent in each lowside or highside power transistor. overcurrent failure I > 2A
OV UV 01 10
These bits indicates failure at VS ( See also parameter Table 8) Voltage at pin VS is too low. Voltage at pin VS is too high.
TSD TW 01 10
These bits indicates temperature failure ( See also parameter Table 6) Only for information set at temperature warning threshold. In case of thermal shutdown all bridges are switched off. It has to reset by bit CLR7.
CLR7
This bit resets all bits to 0 in register7.
5.8
5.8.1
Auxiliary logic blocks
Fault Condition
Logical level at pin D0 represents fault condition. It is valid from first high to low edge of signal CLK up to transfer of data bit D12. Fault bit is an logical OR of: Control and Status Register 6 bit 5 and 6 for Open Load, bit7 reference current failure (RERR) and Control and Status Register 7 bit 0 to bit 7 for Overcurrent, bit 8 and 9 failure at VS (UV,OV) and bit 10 and bit 11 during high temperature (TW,TSD)
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5 SPI - Control and Status Registers
5.8.2
SPI communication monitoring
At the rising edge of the CSN signal the contents of the shift register will be transferred to the selected data register. A counter monitors proper SPI communication. It counts rising edges at pin CLK. The writing to the register is only enabled if exactly 16 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame. SPI communication can be checked by loading a command twice and then answer at pin DO must be same.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.
5.8.3
PWM monitoring for stall detection
Control registers 4, 5, and 3 contain bits D0-D7, use for setting a stall detection threshold. The value in this set of bits determine the minimum time for current rise over one quadrant of motor driving. D7-D0 is compared with the sum of the rise times over one quadrant. When the sum is less than the value stored in D7-D0 the ST bit (register6 bit 8) is set to a logic "1". The PWM pin reflects the PWM control signal of the load current in bridge A. This is so after power on when the SST bit (register 6, bit11) is reset to a logic "0". If this bit is set to a logical "1" then status of the ST bit 8 is mirrored to pin PWM. This provides stall detection without the need of reading register 6 through the SPI bus.
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6 Logic with SPI - Electrical Characteristics
L9942
6
Logic with SPI - Electrical Characteristics
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, Tj = -40 to 150 C, IREF = -200 A, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.
6.1
Table 14.
Symbol Vin L Vin H Vin Hyst ICSN in ICLK in IDI in ISTEP in REN in Cin (1)
Inputs: CSN, CLK, STEP, EN and DI
Inputs: CSN, CLK, STEP, EN and DI
Parameter input low level input high level input hysteresis pull up current at input CSN pull down current at input CLK pull down current at input DI pull down current at input STEP resistance at input EN to GND input capacitance at input CSN, CLK, DI and PWM Test Condition VCC = 5 V VCC = 5 V VCC = 5 V VCSN = VCC-1.5 V, VCLK = 1.5 V VDI = 1.5 V VSTEP = 1.5 V VEN in = VCC 0 V < VCC < 5.3 V 0.5 -50 10 10 10 110 10 -25 25 25 25 -10 50 50 50 510 15 Min. 1.5 Typ. 2.0 3.0 3.5 Max. Unit V V V A A A A k pF
(1) Parameter guaranteed by design.
6.2
Table 15.
DI timing
DI timing (see Figure 11 and Figure 13) (2)
Parameter clock period clock high time clock low time CSN set up time, CSN low before rising edge of CLK CLK set up time, CLK high before rising edge of CSN DI set up time DI hold time rise time of input signal DI, CLK, CSN Test Condition VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V VCC = 5 V Min. 250 100 100 100 100 50 50 25 25 Typ. Max. Unit ns ns ns ns ns ns ns ns ns
Symbol tCLK tCLKH tCLKL tset CSN tset CLK tset DI thold DI tr in tf in
fall time of input signal DI, CLK, CSN VCC = 5 V
(2) DI timing parameters tested in production by a passed/failed test: Tj=-40C/+25C: SPI communication @5MHz; T j=+125C: SPI communication @4.25MHz
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6 Logic with SPI - Electrical Characteristics
6.3
Table 16.
Outputs: DO, PWM
Outputs: DO, PWM
Parameter output low level Test Condition VCC = 5 V, ID = 2 mA Min. Typ. 0.2 Max. 0.4 Unit V
Symbol VDOoutL VPWMoutL VDOoutH
output high level VPWMoutH IDOoutLK IPWMoutLK tristate leakage current
VCC = 5 V, ID = -2 mA VCSN = VCC, 0 V < VDO < VCC Register3bit5=1 (NPWM) 0 V < VPWM < VCC
VCC 0.4 -10
VCC 0.2 10
V
A
tristate leakage current
-10
10
A
Cout (1)
tristate input capacitance
VCSN = VCC, 0 V < VCC < 5.3 V
10
15
pF
6.4
Table 17.
Output: DO timing
Output: DO timing (see Figure 12 and Figure 13) Parameter
DO rise time DO fall time
Symbol
tr DO tf DO ten DO tri L tdis DO L tri ten DO tri H tdis DO H tri td DO
Test Condition
CL = 100 pF, Iload = -1 mA CL = 100 pF, Iload = 1 mA
Min.
Typ.
50 50 50 50 50 50
Max.
100 100 250 250 250 250
Unit
ns ns ns ns ns ns
DO enable time from tristate to low CL = 100 pF, Iload = 1 mA pulllevel up load to VCC DO disable time from low level to tristate DO enable time from tristate to high level DO disable time from high level to tristate DO delay time CL = 100 pF, Iload = 4 mA pullup load to VCC CL = 100 pF, Iload = -1 mA pulldown load to GND CL = 100 pF, Iload = -4 mA
pull-down load to GND
VDO < 0.3 VCC, VDO > 0.7 VCC, CL = 100 pF
50
250
ns
6.5
Table 18.
CSN timing
CSN timing
Parameter Test Condition Transfer of SPI-command to Input Register Min. 2 Typ. Max. Unit s
Symbol
tCSN_HI,min (1) CSN high time, active mode
27/37
6 Logic with SPI - Electrical Characteristics
L9942
6.6
Table 19.
Symbol
STEP timing
STEP timing
Parameter Test Condition Min. 2 Typ. Max. Unit s
tSTEPmin (1) STEP low or high time
(1) Parameter guaranteed by design.
Figure 10. Transfer Timing Diagram
t CSN high to low: DO enabled
CSN_HI,min
CSN
time
CLK
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15
0
1
time
DI: data will be accepted on the rising edge of CLK signal actual data
new data
D5 D4 D3 D2 D1 D0 A2 A1
time
DI
A2
A1 A0 D12D11 D10 D9 D8 D7 D6
DO: data will change on the falling edge of CLK signal status information
DO
D12D11 D10 D9 D8 D7 D6
D5 D4 D3 D2
D1 D0
time
fault bit
CSN low to high: actual data is transfered to registers old data
fault bit actual data
time
Control and Status Register
Figure 11. Input Timing
CSN t set CSN t CLKH
t CLK t
set CLK
0.8 VCC 0.2 VCC
CLK t set DI t hold DI t CL KL
0.8 VCC 0.2 VCC
0.8 VCC DI Valid Valid 0.2 VCC
28/37
L9942
Figure 12. SPI - DO Valid Data Delay Time and Valid Time
6 Logic with SPI - Electrical Characteristics
tf in
t r in 0.8 VCC 0.5 VCC 0.2 VCC t r DO
CLK
DO (low to high) td DO DO (high to low) t f DO
0.8 VCC 0.2 VCC
0.8 VCC 0.2 VCC
Figure 13. DO Enable and Disable Time
t f in
t r in
CSN
0 .8 V C C 50% 0 .2 V C C
DO p u ll - u p lo a d to V C C C L = 100 pF
50%
ten
D O tri L
t d is
D O L tri
DO p u ll- d o w n lo a d t o G N D C L = 100 pF ten
D O tri H
50%
t d is
D O H tri
29/37
6 Logic with SPI - Electrical Characteristics
L9942
Figure 14. Timing of Status Bit 0 (Fault Condition)
C S N h ig h t o l o w a n d C L K s t a y s lo w : s t a t u s in f o r m a t i o n o f d a t a b it 0 ( f a u lt c o n d it io n ) is t r a n s f e r e d t o D O
CSN t im e CLK t im e DI t im e
D I: d a ta is n o t a c c e p te d
DO
0t im e
D O : s t a t u s in f o r m a t io n o f d a t a b it 0 ( f a u lt c o n d it i o n ) w ill s t a y a s l o n g a s C S N is lo w
30/37
L9942
7 Appendix
7
7.1
Appendix
Stall Detection
The L9942 contains logic blocks designed to detect a motor stall caused by excessive mechanical load. During a motor stall condition the load current rises much faster than during normal operation. The L9942 measures this time and compares it to a programmed value. This is done by summing the PWM on times for one full quadrant. For a full wave stepping this is just one value (step 0). For microstepping this includes 8 separate values added together, one for each step. This measurement is only done on phase A during the quadrants where the current is increasing naturally (quadrants 1 and 3 of Figure 15); e.g. stall detection is active during phase counter values 1 to 8 and 17 to 24 for DIR=0. During the quadrants where the current is decreasing fast decay recirculation interferes with accurate measurement of this time. If the sum of the PWM on time is less than a programmed threshold stored in D0-D7, stall is detected and indicated as a logic "1" in the stall (ST) bit found in register 6 bit 8 (Figure 15 bottom). If bit 11 of register 6 is set to logical "1" then the ST bit is mirrored to the PWM pin providing detection externally. The register values DT7-DT0 store the threshold value in 16us intervals. These bits can be found interstitially in register 3 (D0, D1), register4 (D2, D3, D4) and register5 (D5, D6, D7). Care should be taken when deciding the threshold timing. Motor current slew rates are dependant on the driving voltage, the actual speed of the motor, the back EMF of the motor as well as the motor and the inductance. Be sure to set your threshold well away from what can be seen in normal operation at any temperature.
7.2
Load Current Control and Detection of Overcurrent (Shortages at Outputs)
The L9942 controls load current in the two full bridges by using a pulls with modulation (PWM) regulator. The mirrored output current of active HS switch is compared with a programmed reference current (e.g. in figure A2 HSA1 and HSB2). Bridge is switched off if current has exceeded the programmed limit value. A second comparator of the related LS switch uses the mirrored load current to detect an overcurrent to ground during ON state of bridges (e.g. in Figure 16 LSA2 and LSB1). The event of shortage from output to supply voltage VS is detectable, but short current between outputs is limited through PWM controller and so an overcurrent failure will not occur. Load currents decrease more or less fast during OFF state of bridges depending on selected decay mode. Slow decay mode is realised by activating the HS switches of the bridge and current comparator has as new reference the overcurrent limit. A shortage to ground can be detected, but not between the outputs. Is it recommended to use the different fast decay modes too, especially in period if the load current has to reduce from step to step. The duration of fast decay can set by fixed time ore that it depends on the comparator signal utilising the second current mirror at LS switch. There can be monitored the undershoot of bridge current during OFF state.
31/37
7 Appendix
L9942
Fast decay can be seen as switching the bridge in opposite direction, if it is compared to ON state before. The load current control at HS switch is not used, but the comparator is still active. The reference value is changed to overcurrent limit and a shortage to ground or now between the outputs too will result in a signal. The internal filter time of at least 4 us will inhibit the signal in many applications. Then you can use the mode "auto decay without any delay time" (On Section 5.1 on page 21 mode 100). On page 34 you can find in the lower part of Figure 3 the phase counter values, when fast decay as only part of mixed decay is used and the shortages can be detected during a longer time. After this it is signalised in register 7 as overcurrent in HS switch (e.g. in Figure 17 HSA1). Figure 15. Stall Detection
Load Current Rising During High Speed
Counter value is above threshold value.
PWM activ detection Stall Time Threshold
Register 5 Register 4 Reg3 bit7 bit6 bit5 bit7 bit6 bit5 bit7 bit6
D7 D6 D5 D4 D3 D2 D1 D0
16us *
Time
PWM activ detection
PWM activ detection
Stall Threshold PWM activ counter
Stall Threshold PWM activ counter
No Stall Signal
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Phase Counter
0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Activ sampling and threshold
01234567876543210123456787654321
Current Driver A
Adress of Current Profile Entry
01234567876543210123456787654321
Activ sampling and threshold
Current Driver A
Current Driver B
87654321012345678765432101234567
Current Driver B
Adress of Current Profile Entry
87654321012345678765432101234567
STEP Signal
Micro Stepping Mode: DIR=0
Micro Stepping Mode: DIR=1
Load Current Rising During Low Speed or Stall
PWM activ detection
Counter value is below threshold value.
PWM activ detection PWM activ detection
Time Stall Threshold
PWM activ counter Stall Threshold
PWM activ counter
Stall Signal
Stall Signal
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Phase Counter
0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Activ sampling and threshold
01234567876543210123456787654321
Current Driver A
Adress of Current Profile Entry
01234567876543210123456787654321
Activ sampling and threshold
Current Driver A
Current Driver B
87654321012345678765432101234567
Current Driver B
Adress of Current Profile Entry
87654321012345678765432101234567
STEP Signal
Micro Stepping Mode: DIR=0
Micro Stepping Mode: DIR=1
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L9942
Figure 16. Reference Generation for PWM Control (Switch On)
1
7 Appendix
UP/Down Count by 1,2,4,8
PhaseCounter 1
Register 0
Decay Mode Slew Rate SR1 SR0
Counter value changes after an signal at STEP to next one depending on selected stepping mode described in figure 3 (e.g. during micro stepping to value 2) .
StepMode DIR
0 0
0
0
0
0
1
DM2
DM1
DM0
0
STEP
0
0
0
012301230123
A2
MUX
A1
MUX
A0
MUX
Address Calculation Phase A
Adr A3=0 A[3..0] Adr A3=1 neg(A[3..0])
A3
A2
A1
A0
Phase B
Adr A3=0 neg(A[3..0]) A3=1 Adr A[3..0]
PWM Control With HS Current Monitoring Overcurrent Detection At LS Switch
Current-Profile Table stored in register2, ...6
9 5
1
1
1
1
1
Profile 8
5
Phase Counter
0
1
1 1 1 1 0
1
1 1 0 0 1
1
1 0 1 0 1
1
0 1 1 0 0
0
1 0 0 1 0
Profile 7
5
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Current Driver A
Adress of Current Profile Entry Phase A 1
Profile 6
5
Profile 5
5
0
234567876543210123456787654321
Profile 4
5
Profile 3
5
Profile 2
5
Current Driver B
Adress of Current Profile Entry Phase B
8
7
654321012345678765432101234567
0
0
0
0
1
0
1
0
0
0
Profile 1
5
Profile 0
5
STEP Signal
Register 1
DAC Scale DAC Phase B DAC Phase A
DI
0
0
0
1
1
1
1
0
0
0
1
1
0 LIMIT HSA1 2mA 2mA
+
HS Current Monitoring (Load control)
IQA1LIM 1000 HS1 on QA1
95 mA
100mA * 30/31 = 91.9mA
100mA * 6/31 = 18.4mA
I
5 bit DAC Phase B
LIMIT B
5 bit DAC Phase A
I LIMIT A
I REF REF 200 uA
DAC Full Scale
I MAX
+ -
+
+
IA
2mA
QB1
+
LS Current Monitoring (Overcurrentl)
2mA OC LSB1
+ -
LS1 on
2mA IB OC 2mA
LSA2
QA2
+ -
+ -
LS2 on
LIMIT HSB2
HS Current Monitoring (Load control)
+
2mA 2mA
IQA2LIM 1000
HS2on QB2
-
+
LS Current Monitoring (Overcurrent)
+ -
+ -
33/37
7 Appendix
L9942
Figure 17. Reference Generation for PWM Contro (Decay)l
1
UP/Down Count by 1,2,4,8
PhaseCounter
1
Register 0
Decay Mode Slew Rate SR1 SR0
Counter value changes after an signal at STEP to next one depending on selected stepping mode described in figure 1.2 (e.g. during micro stepping to value 2) .
StepMode DIR
0 0
0
0
0
0
1
DM2
DM1
DM0
0
STEP
0
0123
0
0123
0
0123
Auto Decay Mixed Decay Fast and Slow Decay
A2
MUX
A1
MUX
A0
MUX
Address Calculation Phase A
Adr A3=0 A[3..0] Adr A3=1 neg(A[3..0])
A3
A2
A1
A0
Slow Decay
A3=1 Adr A[3..0]
Phase B
Adr A3=0 neg(A[3..0])
Current-Profile Table stored in register2, ...6
9 5
1
1
1
1
1
Profile 8
5
Phase Counter
0
1
1 1 1 1 0
1
1 1 0 0 1
1
1 0 1 0 1
1
0 1 1 0 0
0
1 0 0 1 0
Profile 7
5
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Current Driver A
Adress of Current Profile Entry Phase A 1
Profile 6
5
Profile 5
5
0
234567876543210123456787654321
Profile 4
5
Profile 3
5
Profile 2
5
Current Driver B
Adress of Current Profile Entry Phase B
8
7
654321012345678765432101234567
0
0
0
0
1
0
1
0
0
0
Profile 1
5
Profile 0
5
STEP Signal
Register 1
DAC Scale DAC Phase B DAC Phase A
DI
0
0
0
1
1
1
1
0
0
0
1
1
0 OC
HSA1 +
HS Current Monitoring (Overcurrent)
HS1 on QA1 2mA 2mA
95 mA
95mA * 30/31 = 91.9mA
100mA * 6/31 = 18.4mA
I
5 bit DAC Phase B
LIMIT B
5 bit DAC Phase A
I LIMIT A
I REF REF 200 uA
+ -
DAC Full Scale
I MAX
HS Current Monitoring (Overcurrent)
OC
HSB1
+
2mA 2mA
IQB1 1000
HS1 on QB1
-
+
Slow Decay
HS2 on QA2
IA
OC
+ -
HSB1
+
2mA
+ +
Fast Decay
IB
2mA
+ -
+
LS Current Monitoring (Load Control)
2mA 2mA
QB2
HS Current Monitoring (Overcurrent)
-
+ -
LS2on
LIMIT LSB2
-
+
34/37
L9942
8 Package information
8
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 18. PowerSSO-24 Mechanical Data & Package Dimensions
mm DIM. MIN. A A2 a1 b c D E e e3 G G1 H k h L N X Y 4.1 6.5 0.55 10.1 5 0.4 0.85 10 4.7 7.1 0.161 0.256 0.021 2.15 2.15 0 0.33 0.23 10.10 7.4 0.8 8.8 0.1 0.06 10.5 0.398 5 0.016 0.033 10 0.185 0.279 TYP. MAX. 2.47 2.40 0.075 0.51 0.32 10.50 7.6 0.013 0.009 0.398 0.291 0.031 0.346 0.004 0.002 0.413 MIN. 0.085 0.085 TYP. MAX. 0.097 0.094 0.003 0.02 0.012 0.413 0.299 inch
OUTLINE AND MECHANICAL DATA
PowerSSO-24 (Exposed Pad)
35/37
9 Revision history
L9942
9
Revision history
Date 7-Nov-2005 Revision 1 Initial release. Changes
36/37
L9942
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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